P. Nordholz, D. Treytnar, H. Grabinski, J. Otterstedt, D. Niggemeyer, U. Arz and T. W. Williams
Abstract
The SIA Roadmap predicts a very aggressive path of technologies from 0.35 µm
to 0.10 µm technology design. Increasing frequencies together with decreasing
geometries lead to a number of issues which need to be examined. Testing is
clearly one main issue. Another area of concern is that of signal integrity of
the interconnects.
The interconnects must not only be analyzed with regard to opens and shorts but
also with regard to the signal delays. In addition, it has to be considered that
the signal delay (i.e. the time when the signal crosses the switching threshold
of the following gate) on a certain line within a bus system depends on the set
of input signals of all bus lines. Furthermore, hazards can occur. Both effects
are due to coupling and can lead to an incorrect function of the whole circuit..
This poster has been published in:
This document is available as a PostScript File (330K) and PDF (82K) .