Petra Nordholz, Dieter Treytnar, Jan Otterstedt, Hartmut Grabinski, Dirk Niggemeyer, T. W. Williams
Abstract
The SIA Roadmap shows a very aggressive drive to deep submicron designs. A
significant corner stone in the industries' ability to utilize this tremendous
capabilities is the usage of reusable cores. When employing cores, one must be
sensitive to the quality of the interconnects which will carry signals between
cores and the ASIC portion of the network. In this work we will use an extremely
accurate line simulator which solves the transmission line equations derived
from Maxwell's equations for the simulation of line systems. We will show that
the coupling between bus lines is significant, since the signal delay can be
increased and even hazards can occur. Furthermore, these effects depend on the
set of input signals of all bus lines and the skew between the individual input
signals. The lines' cross sections are taken from the SIA Roadmap going from
0.35 µm technology design down to 0.10 µm technology design.
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