Petra Nordholz, Dieter Treytnar, Jan Otterstedt, Hartmut Grabinski, Dirk Niggemeyer, Uwe Arz, T.W.Williams

Deep Submicron Interconnect Coupling with Cores

Abstract
The SIA Roadmap shows a very aggressive drive to deep submicron designs. A significant corner stone in the industries' ability to utilize this tremendous capabilities is the usage of reusable cores. When employing cores, one must be sensitive to the quality of the interconnects which will carry signals between cores and the ASIC portion of the network. In this work we will use an extremely accurate line simulator which solves the telegraphers equations derived from Maxwell's equations for the simulation of line systems.  We will show that the coupling between bus lines is significant, since the signal delay can be increased and even hazards can can occur. Furthermore, these effects depend on the set of input signals of all bus lines. The lines' crossections will be taken from the SIA Roadmap going 0.35µm technology design down to 0.10µm technology design.    

This paper has been published in:

• 1st IEEE International Workshop on Testing Embedded Core-based Systems, TECS 97, November 5-6, 1997.

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